1. Field of the Invention
The present invention relates to a ball grid array (BGA) package of a chip scale, and more particularly, to a BGA package for providing a constant internal voltage by forming an auxiliary routing configuration on a printed circuit board (PCB) substrate of the BGA package.
2. Description of the Related Art
As semiconductor devices are further minimized in size, the integration density of corresponding semiconductor integrated circuit devices increases, which in turn increases the number of input/output pins. As a result, the ball grid array (BGA) package has been developed as a type of semiconductor package.
When compared with conventional plastic lead frame packages, the BGA package occupies substantially less area when mounted on a main board, while at the same time the electrical characteristics of the BGA package are considered to be quite excellent.
The BGA package differs from the plastic package in that, instead of a lead frame, the BGA package electrically connects a semiconductor chip and the main board via a circuit board, which is formed by external pads, such as a circuit routing configuration, and solder balls.
Since the external pads are formed on the surface of the circuit board that is opposite to the surface where the semiconductor chip is attached, the area of the BGA package can be reduced relative to the conventional plastic package.
FIG. 1 illustrates a conventional routing method of power lines in a chip. In FIG. 1, a semiconductor chip 10 (depicted as a memory chip) includes internal voltage lines 16, bonding pads 15, and banks or regions 11, 12, 13, and 14. The internal voltage lines 16 supply internal voltages, that is, a word line driving voltage (Vpp), a bit line driving voltage (Vbl), or a back bias voltage (Vbb) to each of the regions 11, 12, 13, and 14.
As the semiconductor devices become more highly integrated, the size of transistors used in a memory cell or a peripheral circuit decreases. However, the current required for each of the transistors does not decrease. As a result, the internal voltage line width for supplying the voltage effectively increases, relative to the now reduced-sized memory cell or peripheral circuit.
This problem is demonstrated by the following example. The level of the Vpp varies according to the position of the enabled word line, and the voltage dip of the Vpp is not identical in all parts of the chip 10. Thus, conventionally, in order to eliminate a difference in the Vpp level, the internal voltage line width for supplying the Vpp is increased, thereby decreasing a resistance R in the internal voltage line. However, if the internal voltage line width for supplying the internal voltage is increased, the size of the chip is also undesirably increased, thereby increasing production costs.
On the other hand, if the internal voltage line width for supplying the internal voltage is decreased, the size of the chip is also decreased, but the level of the internal voltage in regions A/B and regions C/D is varied, and this adversely affects chip operation.
FIG. 2 is a plan view of a conventional ball grid array (BGA) package. The BGA package includes a semiconductor chip 10 having a plurality of bonding pads 15, an opening 29 for exposing the bonding pads 15, a substrate 20 having a plurality of substrate pads 22, and a plurality of connectors 21, connecting the substrate pads 22 to the bonding pads 15.
The above described problem, in which the internal voltage line width for supplying an internal voltage is decreased and the level of the internal voltage in the regions A/B and the regions C/D is varied, cannot be compensated for in the conventional BGA package. Therefore, a need exits for a BGA package that can supply a constant internal voltage.
To solve the above problems, it is an object of the present invention to provide a ball grid array (BGA) package which supplies a constant internal voltage using an auxiliary routing configuration on a printed circuit board (PCB) of the BGA package.
Accordingly, to achieve the above object, according to one aspect of the present invention, there is provided a ball grid array (BGA) package. The BGA package includes a substrate having an opening, a plurality of pads attached to an upper surface of the substrate, a semiconductor chip having a plurality of bonding pads and attached to a lower surface of the substrate, an internal connection mechanism for connecting at least one of the plurality of bonding pads to at least one pad via the opening, and a filling material for filling the opening to protect the bonding pads and the internal connection mechanism. At least one of the plurality of bonding pads is electrically connected to at least one other bonding pad via an auxiliary routing configuration of the substrate.
Preferably, the at least one bonding pad and the at least one other bonding pad may be one of an internal voltage converter (IVC), Vpp, Vbb, and Vbl pads.
In another aspect of the present invention, the BGA package includes an internal routing configuration in the chip, for commonly connecting bonding pads to an internal voltage of the chip, and an auxiliary routing configuration of the PCB connected to the bonding pads. The resistance of the internal routing configuration is larger than that of the auxiliary routing configuration.